19 #ifndef PORT_ATOMIC_POINTER_H_
20 #define PORT_ATOMIC_POINTER_H_
23 #ifdef LEVELDB_CSTDATOMIC_PRESENT
30 #include <libkern/OSAtomic.h>
33 #if defined(_M_X64) || defined(__x86_64__)
34 #define ARCH_CPU_X86_FAMILY 1
35 #elif defined(_M_IX86) || defined(__i386__) || defined(__i386)
36 #define ARCH_CPU_X86_FAMILY 1
37 #elif defined(__ARMEL__)
38 #define ARCH_CPU_ARM_FAMILY 1
39 #elif defined(__ppc__) || defined(__powerpc__) || defined(__powerpc64__)
40 #define ARCH_CPU_PPC_FAMILY 1
48 #if defined(OS_WIN) && defined(COMPILER_MSVC) && defined(ARCH_CPU_X86_FAMILY)
51 #define LEVELDB_HAVE_MEMORY_BARRIER
54 #elif defined(OS_MACOSX)
55 inline void MemoryBarrier() {
58 #define LEVELDB_HAVE_MEMORY_BARRIER
61 #elif defined(ARCH_CPU_X86_FAMILY) && defined(__GNUC__)
62 inline void MemoryBarrier() {
65 __asm__ __volatile__(
"" : : :
"memory");
67 #define LEVELDB_HAVE_MEMORY_BARRIER
70 #elif defined(ARCH_CPU_X86_FAMILY) && defined(__SUNPRO_CC)
71 inline void MemoryBarrier() {
74 asm volatile(
"" : : :
"memory");
76 #define LEVELDB_HAVE_MEMORY_BARRIER
79 #elif defined(ARCH_CPU_ARM_FAMILY) && defined(__linux__)
80 typedef void (*LinuxKernelMemoryBarrierFunc)(void);
91 inline void MemoryBarrier() {
92 (*(LinuxKernelMemoryBarrierFunc)0xffff0fa0)();
94 #define LEVELDB_HAVE_MEMORY_BARRIER
97 #elif defined(ARCH_CPU_PPC_FAMILY) && defined(__GNUC__)
98 inline void MemoryBarrier() {
101 asm volatile(
"sync" : : :
"memory");
103 #define LEVELDB_HAVE_MEMORY_BARRIER
108 #if defined(LEVELDB_HAVE_MEMORY_BARRIER)
129 #elif defined(LEVELDB_CSTDATOMIC_PRESENT)
132 std::atomic<void*>
rep_;
137 return rep_.load(std::memory_order_acquire);
140 rep_.store(v, std::memory_order_release);
143 return rep_.load(std::memory_order_relaxed);
146 rep_.store(v, std::memory_order_relaxed);
151 #elif defined(__sparcv9) && defined(__GNUC__)
160 __asm__ __volatile__ (
161 "ldx [%[rep_]], %[val] \n\t"
162 "membar #LoadLoad|#LoadStore \n\t"
169 __asm__ __volatile__ (
170 "membar #LoadStore|#StoreStore \n\t"
171 "stx %[v], [%[rep_]] \n\t"
173 : [rep_]
"r" (&rep_), [v]
"r" (v)
181 #elif defined(__ia64) && defined(__GNUC__)
190 __asm__ __volatile__ (
191 "ld8.acq %[val] = [%[rep_]] \n\t"
199 __asm__ __volatile__ (
200 "st8.rel [%[rep_]] = %[v] \n\t"
202 : [rep_]
"r" (&rep_), [v]
"r" (v)
212 #error Please implement AtomicPointer for this platform.
216 #undef LEVELDB_HAVE_MEMORY_BARRIER
217 #undef ARCH_CPU_X86_FAMILY
218 #undef ARCH_CPU_ARM_FAMILY
219 #undef ARCH_CPU_PPC_FAMILY
224 #endif // PORT_ATOMIC_POINTER_H_
void * Acquire_Load() const
void NoBarrier_Store(void *v)
void * NoBarrier_Load() const
void Release_Store(void *v)